Many integrated circuits that perform multiple functions require transistors having different operating characteristics on the same chip. Specifically, transistors having different gate dielectric (oxide) thicknesses are needed on the same chip to accommodate different voltage requirements.
One prior art technique for fabricating an integrated circuit having two different gate dielectric thicknesses that correspond to two different device areas involves a single photolithographic process. According to the technique, a first gate dielectric is formed on a substrate over two device areas, with the two device areas being electrically separated by field oxide. A photoresist mask is used to protect the gate dielectric over the first device area, while the gate dielectric over the second device area is removed using known etching techniques. The photoresist mask is then removed from the first gate dielectric and a second gate dielectric is formed. In the process of forming the second gate dielectric on the second device area, the thickness of the first gate dielectric is increased by approximately the same thickness as the second gate dielectric. The result of the process is a first gate dielectric having a first thickness and a second gate dielectric having a second thickness. Although the fabrication process is able to generate two different gate dielectrics with a single photolithographic step, the process requires direct contact between the first gate dielectric and the photoresist. Photoresist is known to be a significant source of contamination to gate dielectrics and, therefore, it is preferable to avoid direct contact between gate dielectrics and photoresist.
A fabrication technique that does not involve direct contact between gate dielectrics and photoresist is disclosed in U.S. Pat. No. 5,668,035, entitled "Method for Fabricating a Dual-Gate Dielectric Module for Memory with Embedded Logic Technology," issued to Fang et al. (hereinafter Fang). In accordance with the Fang fabrication technique, a first gate oxide (dielectric) layer is formed on two device areas of a substrate. A first polysilicon layer is deposited onto the first gate oxide layer that exists over the first and second device areas. The first polysilicon layer is then removed over the first device area utilizing a first photolithographic step. The first gate oxide layer is also removed over the first device area and a new, thinner, gate oxide layer is deposited over the first device area. A second polysilicon layer is deposited over both the first and second device areas. Portions of the second polysilicon layer are removed utilizing a second photolithographic step in order to even out the thicknesses of the first and second polysilicon layers that exist above the two gate oxide layers. Further known processing techniques are utilized to complete the desired devices. Although the Fang method avoids applying photoresist directly onto a gate oxide layer, the Fang method requires two photolithographic steps to create the dual gate dielectric layers. Photolithographic steps are a significant cost in the fabrication of semiconductor devices and, therefore, it is preferable to minimize the number of photolithographic steps that are required.
As a result of the stated shortcomings of the prior art techniques for fabricating dual gate dielectric layers, what is needed is a method for fabricating dual gate dielectric layers that avoids direct contact between gate oxide layers and photoresist, while minimizing the number of photolithographic processing steps that are required.